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K7B803625B K7B801825B
Document Title
256Kx36 & 512Kx18 Synchronous SRAM
256Kx36 & 512Kx18-Bit Synchronous Burst SRAM
Revision History
Rev. No. 0.0 0.1 0.2 1.0 History Initial draft Add x32 org part and industrial temperature part 1. change scan order(1) form 4T to 6T at 119BGA(x18) 1. Final spec release 2. Change ISB2 form 50mA to 60mA Change ordering information( remove 225MHz at SPB) 1. Delete 119BGA package 1. Remove x32 organization 2. Remove -85 speed bin Draft Date May. 18 . 2001 Aug. 11. 2001 Aug. 28. 2001 Nov. 16. 2001 Remark Preliminary Preliminary Preliminary Final
2.0 2.1 3.0
April. 01. 2002 April. 04. 2003 Nov. 17. 2003
Final Final Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
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Nov. 2003 Rev 3.0
K7B803625B K7B801825B
256Kx36 & 512Kx18 Synchronous SRAM
8Mb SB/SPB Synchronous SRAM Ordering Information
Org. Part Number K7B801825B-QC(I)65/75 512Kx18 K7A801800B-QC(I)16/14 K7A801809B-QC(I)25 K7B803625B-QC(I)65/75 256Kx36 K7A803600B-QC(I)16/14 K7A803609B-QC(I)25 Mode SB SPB(2E1D) SPB(2E1D) SB SPB(2E1D) SPB(2E1D) VDD 3.3 3.3 3.3 3.3 3.3 3.3 Speed FT ; Access Time(ns) Pipelined ; Cycle Time(MHz) 6.5/7.5 ns 167/138 MHz 250 MHz 6.5/7.5 ns 167/138 MHz 250 MHz Q: 100TQFP PKG Temp C: Commercial Temperature Range I: Industrial Temperature Range
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Nov. 2003 Rev 3.0
K7B803625B K7B801825B
256Kx36 & 512Kx18 Synchronous SRAM
256Kx36 & 512Kx18-Bit Synchronous Burst SRAM
FEATURES
* Synchronous Operation. * On-Chip Address Counter. * Self-Timed Write Cycle. * On-Chip Address and Control Registers. * 3.3V+0.165V/-0.165V Power Supply. * I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O * 5V Tolerant Inputs Except I/O Pins. * Byte Writable Function. * Global Write Enable Controls a full bus-width write. * Power Down State via ZZ Signal. * LBO Pin allows a choice of either a interleaved burst or a linear burst. * Three Chip Enables for simple depth expansion with No Data Contention only for TQFP. * Asynchronous Output Enable Control. * ADSP, ADSC, ADV Burst Control Pins. * TTL-Level Three-State Output. * 100-TQFP-1420A * Operating in commeical and industrial temperature range.
GENERAL DESCRIPTION
The K7B803625B and K7B801825B are 9,437,184-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System. It is organized as 256K(512K) words of 36(18) bits and integrates address and control registers, a 2-bit burst address counter and added some new functions for high performance cache RAM applications; GW, BW, LBO, ZZ. Write cycles are internally self-timed and synchronous. Full bus-width write is done by GW, and each byte write is performed by the combination of WEx and BW when GW is high. And with CS1 high, ADSP is blocked to control signals. Burst cycle can be initiated with either the address status processor(ADSP) or address status cache controller(ADSC) inputs. Subsequent burst addresses are generated internally in the systems burst sequence and are controlled by the burst address advance(ADV) input. LBO pin is DC operated and determines burst sequence(linear or interleaved). ZZ pin controls Power Down State and reduces Stand-by current regardless of CLK. The K7B803625B and K7B801825B are fabricated using SAMSUNGs high performance CMOS technology and is available in a 100pin TQFP and Multiple power and ground pins are utilized to minimize ground bounce.
FAST ACCESS TIMES
PARAMETER Cycle Time Clock Access Time Output Enable Access Time Symbol -65 tCYC tCD tOE 7.5 6.5 3.5 -75 8.5 7.5 3.5 -85 Unit 10 8.5 4.0 ns ns ns
LOGIC BLOCK DIAGRAM
CLK LBO CONTROL REGISTER ADV ADSC
BURST CONTROL LOGIC
BURST ADDRESS COUNTER A0~A1
A0~A1
256Kx36 , 512Kx18 MEMORY ARRAY
ADSP
A0~A17 or A0~A18
ADDRESS REGISTER
A2~A17 or A2~A18
CS1 CS2 CS2 GW BW WEx (x=a,b,c,d or a,b) OE ZZ
DATA-IN REGISTER CONTROL REGISTER
CONTROL LOGIC
OUTPUT BUFFER
DQa0 ~ DQd7 or DQa0 ~ DQb7 DQPa ~ DQPd DQPa,DQPb
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Nov. 2003 Rev 3.0
K7B803625B K7B801825B
PIN CONFIGURATION(TOP VIEW)
WEd WEb WEc
256Kx36 & 512Kx18 Synchronous SRAM
ADSC ADSP
WEa
A6
ADV 83
CLK
CS1
CS2
CS2
VDD
GW
VSS
BW
OE
A7
A8 82
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
VSS
A5
A4
A3
A2
A1
A0
A17
A10
A12
A13
A14
A15
LBO
N.C.
N.C.
VDD
N.C.
PIN
SYMBOL A0 - A17 PIN NAME Address Inputs TQFP PIN NO. SYMBOL VDD VSS N.C. DQa0~a7 DQb0~b7 DQc0~c7 DQd0~d7 DQPa~Pd VDDQ VSSQ PIN NAME Power Supply(+3.3V) Ground No Connect Data Inputs/Outputs TQFP PIN NO. 15,41,65,91 17,40,67,90 14,16,38,39,42,66 52,53,56,57,58,59,62,63 68,69,72,73,74,75,78,79 2,3,6,7,8,9,12,13 18,19,22,23,24,25,28,29 51,80,1,30 4,11,20,27,54,61,70,77 5,10,21,26,55,60,71,76 32,33,34,35,36,37,43 44,45,46,47,48,49,50 81,82,99,100 83 ADV Burst Address Advance Address Status Processor 84 ADSP Address Status Controller 85 ADSC 89 Clock CLK 98 Chip Select CS1 97 Chip Select CS2 92 Chip Select CS2 93,94,95,96 WEx(x=a,b,c,d) Byte Write Inputs 86 Output Enable OE 88 Global Write Enable GW 87 Byte Write Enable BW 64 Power Down Input ZZ 31 Burst Mode Control LBO
Output Power Supply (2.5V or 3.3V) Output Ground
Notes : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. 2. The pin 42 is reserved for address bit for the 16Mb .
A16
A11
50
DQPc DQc0 DQc1 VDDQ VSSQ DQc2 DQc3 DQc4 DQc5 VSSQ VDDQ DQc6 DQc7 N.C. VDD N.C. VSS DQd0 DQd1 VDDQ VSSQ DQd2 DQd3 DQd4 DQd5 VSSQ VDDQ DQd6 DQd7 DQPd
81
A9
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100 Pin TQFP
(20mm x 14mm)
K7B803625B(256Kx36)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DQPb DQb7 DQb6 VDDQ VSSQ DQb5 DQb4 DQb3 DQb2 VSSQ VDDQ DQb1 DQb0 VSS N.C. VDD ZZ DQa7 DQa6 VDDQ VSSQ DQa5 DQa4 DQa3 DQa2 VSSQ VDDQ DQa1 DQa0 DQPa
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Nov. 2003 Rev 3.0
K7B803625B K7B801825B
PIN CONFIGURATION(TOP VIEW)
256Kx36 & 512Kx18 Synchronous SRAM
ADSC
ADSP
WEb
WEa
A6
ADV 83
N.C.
N.C.
CLK
CS1
CS2
CS2
VDD
GW
VSS
BW
OE
A7
A8 82
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
81
A9
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
VSS
A5
A4
A3
A2
A1
A0
A18
A12
A13
A14
A15
A16
LBO
N.C.
N.C.
VDD
N.C.
PIN NAME
SYMBOL A0 - A18 PIN NAME Address Inputs TQFP PIN NO. 32,33,34,35,36,37,43 44,45,46,47,48,49,50 80,81,82,99,100 83 84 85 89 98 97 92 93,94 86 88 87 64 31 SYMBOL VDD VSS N.C. PIN NAME Power Supply(+3.3V) Ground No Connect TQFP PIN NO. 15,41,65,91 17,40,67,90 1,2,3,6,7,14,16,25,28,29, 30,38,39,42,51,52,53,56, 57,66,75,78,79,95,96 58,59,62,63,68,69,72,73 8,9,12,13,18,19,22,23 74,24 4,11,20,27,54,61,70,77 5,10,21,26,55,60,71,76
ADV ADSP ADSC CLK CS1 CS2 CS2 WEx OE GW BW ZZ LBO
Burst Address Advance Address Status Processor Address Status Controller Clock Chip Select Chip Select Chip Select Byte Write Inputs Output Enable Global Write Enable Byte Write Enable Power Down Input Burst Mode Control
DQa0 ~ a7 DQb0 ~ b7 DQPa, Pb VDDQ VSSQ
Data Inputs/Outputs
Output Power Supply (2.5V or 3.3V) Output Ground
Notes : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. 2. The pin 42 is reserved for address bit for the 16Mb .
A17
A11
50
N.C. N.C. N.C. VDDQ VSSQ N.C. N.C. DQb0 DQb1 VSSQ VDDQ DQb2 DQb3 N.C. VDD N.C. VSS DQb4 DQb5 VDDQ VSSQ DQb6 DQb7 DQPb N.C. VSSQ VDDQ N.C. N.C. N.C.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100 Pin TQFP
(20mm x 14mm)
K7B801825B(512Kx18)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
A10 N.C. N.C. VDDQ VSSQ N.C. DQPa DQa7 DQa6 VSSQ VDDQ DQa5 DQa4 VSS N.C. VDD ZZ DQa3 DQa2 VDDQ VSSQ DQa1 DQa0 N.C. N.C. VSSQ VDDQ N.C. N.C. N.C.
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Nov. 2003 Rev 3.0
K7B803625B K7B801825B
FUNCTION DESCRIPTION
256Kx36 & 512Kx18 Synchronous SRAM
The K7B803625B and K7B801825B are synchronous SRAM designed to support the burst address accessing sequence of the Power PC based microprocessor. All inputs (with the exception of OE, LBO and ZZ) are sampled on rising clock edges. The start and duration of the burst access is controlled by ADSC, ADSP and ADV and chip select pins. The accesses are enabled with the chip select signals and output enabled signals. Wait states are inserted into the access with ADV. When ZZ is pulled high, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2cycles of wake up time. ZZ pin is pulled down internally. Read cycles are initiated with ADSP(or ADSC) using the new external address clocked into the on-chip address register when both GW and BW are high or when BW is low and WEa, WEb, WEc, and WEd are high. When ADSP is sampled low, the chip selects are sampled active, and the output buffer is enabled with OE. the data of cell array accessed by the current address are projected to the output pins. Write cycles are also initiated with ADSP(or ADSC) and are differentiated into two kinds of operations; All byte write operation and individual byte write operation. All byte write occurs by enabling GW(independent of BW and WEx.), and individual byte write is performed only when GW is high and BW is low. In K7B803625B, a 256Kx36 organization, WEa controls DQa0 ~ DQa7 and DQPa, WEb controls DQb0 ~ DQb7 and DQPb, WEc controls DQc0 ~ DQc7 and DQPc and WEd controls DQd0 ~ DQd7 and DQPd. CS1 is used to enable the device and conditions internal use of ADSP and is sampled only when a new external address is loaded. ADV is ignored at the clock edge when ADSP is asserted, but can be sampled on the subsequent clock edges. The address increases internally for the next access of the burst when ADV is sampled low. Addresses are generated for the burst access as shown below, The starting point of the burst sequence is provided by the external address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state of the LBO pin. When this pin is Low, linear burst sequence is selected. And this pin is High, Interleaved burst sequence is selected.
BURST SEQUENCE TABLE
LBO PIN HIGH First Address Case 1 A1 0 0 1 1 A0 0 1 0 1 A1 0 0 1 1 Case 2 A0 1 0 1 0 A1 1 1 0 0 Case 3 A0 0 1 0 1
(Interleaved Burst)
Case 4 A1 1 1 0 0 A0 1 0 1 0
Fourth Address
BQ TABLE
LBO PIN LOW First Address Case 1 A1 0 0 1 1 A0 0 1 0 1 A1 0 1 1 0 Case 2 A0 1 0 1 0 A1 1 1 0 0 Case 3 A0 0 1 0 1 A1 1 0 0 1
(Linear Burst)
Case 4 A0 1 0 1 0
Fourth Address
Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.
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Nov. 2003 Rev 3.0
K7B803625B K7B801825B
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
CS1 H L L L L L L L X H X H X H X H CS2 X L X L X H H H X X X X X X X X CS2 X X H X H L L L X X X X X X X X ADSP ADSC X L L X X L H H H X H X H X H X L X X L L X L L H H H H H H H H ADV X X X X X X X X L L L L H H H H
256Kx36 & 512Kx18 Synchronous SRAM
WRITE X X X X X X L H H H L L H H L L
CLK
ADDRESS ACCESSED N/A N/A N/A N/A N/A External Address External Address External Address Next Address Next Address Next Address Next Address Current Address Current Address Current Address Current Address
OPERATION Not Selected Not Selected Not Selected Not Selected Not Selected Begin Burst Read Cycle Begin Burst Write Cycle Begin Burst Read Cycle Continue Burst Read Cycle Continue Burst Read Cycle Continue Burst Write Cycle Continue Burst Write Cycle Suspend Burst Read Cycle Suspend Burst Read Cycle Suspend Burst Write Cycle Suspend Burst Write Cycle
Notes : 1. X means "Dont Care".
2. The rising edge of clock is symbolized by .
3. WRITE = L means Write operation in WRITE TRUTH TABLE. WRITE = H means Read operation in WRITE TRUTH TABLE. 4. Operation finally depends on status of asynchronous input pins(ZZ and OE).
WRITE TRUTH TABLE( x36)
GW H H H H H H L BW H L L L L L X WEa X H L H H L X WEb X H H L H L X WEc X H H H L L X WEd X H H H L L X OPERATION READ READ WRITE BYTE a WRITE BYTE b WRITE BYTE c and d WRITE ALL BYTEs WRITE ALL BYTEs
Notes : 1. X means "Dont Care". 2. All inputs in this table must meet setup and hold time around the rising edge of CLK().
WRITE TRUTH TABLE(x18)
GW H H H H H L BW H L L L L X WEa X H L H L X WEb X H H L L X OPERATION READ READ WRITE BYTE a WRITE BYTE b WRITE ALL BYTEs WRITE ALL BYTEs
Notes : 1. X means "Dont Care". 2. All inputs in this table must meet setup and hold time around the rising edge of CLK().
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Nov. 2003 Rev 3.0
K7B803625B K7B801825B
ASYNCHRONOUS TRUTH TABLE
Operation Sleep Mode Read Write Deselected ZZ H L L L L OE X L H X X
256Kx36 & 512Kx18 Synchronous SRAM
I/O STATUS High-Z DQ High-Z Din, High-Z High-Z
Notes 1. X means "Dont Care". 2. ZZ pin is pulled down internally 3. For write cycles that following read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur. 4. Sleep Mode means power down state of which stand-by current does not depend on cycle time. 5. Deselected means power down state of which stand-by current depends on cycle time.
ABSOLUTE MAXIMUM RATINGS*
PARAMETER Voltage on VDD Supply Relative to VSS Voltage on VDDQ Supply Relative to VSS Voltage on Input Pin Relative to VSS Voltage on I/O Pin Relative to VSS Power Dissipation Storage Temperature Operating Temperature Storage Temperature Range Under Bias Commercial Industrial SYMBOL VDD VDDQ VIN VIO PD TSTG TOPR TOPR TBIAS RATING -0.3 to 4.6 VDD -0.3 to VDD+0.3 -0.3 to VDDQ+0.3 1.6 -65 to 150 0 to 70 -40 to 85 -10 to 85 UNIT V V V V W C C C C
*Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING CONDITIONS at 3.3V I/O(0C TA 70C)
PARAMETER Supply Voltage Ground SYMBOL VDD VDDQ VSS MIN 3.135 3.135 0 Typ. 3.3 3.3 0 MAX 3.465 3.465 0 UNIT V V V
* The above parameters are also guaranteed at industrial temperature range.
OPERATING CONDITIONS at 2.5V I/O(0C TA 70C)
PARAMETER Supply Voltage Ground SYMBOL VDD VDDQ VSS MIN 3.135 2.375 0 Typ. 3.3 2.5 0 MAX 3.465 2.9 0 UNIT V V V
* The above parameters are also guaranteed at industrial temperature range.
CAPACITANCE*(TA=25C, f=1MHz)
PARAMETER Input Capacitance Output Capacitance
*Note : Sampled not 100% tested.
SYMBOL CIN COUT
TEST CONDITION VIN=0V VOUT=0V
MIN -
MAX 5 7
UNIT pF pF
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Nov. 2003 Rev 3.0
K7B803625B K7B801825B
Parameter Input Leakage Current(except ZZ) Output Leakage Current Operating Current Symbol IIL IOL ICC
256Kx36 & 512Kx18 Synchronous SRAM
DC ELECTRICAL CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0C to +70C)
Test Conditions VDD=Max ; VIN=VSS to VDD Output Disabled, Vout=VSS to VDDQ Device Selected, IOUT=0mA, ZZVIL , Cycle Time tCYC Min Device deselected, IOUT=0mA, ISB Standby Current ZZVIL, f=Max, All Inputs0.2V or VDD-0.2V ISB1 ISB2 Output Low Voltage(3.3V I/O) Output High Voltage(3.3V I/O) Output Low Voltage(2.5V I/O) Output High Voltage(2.5V I/O) Input Low Voltage(3.3V I/O) Input High Voltage(3.3V I/O) Input Low Voltage(2.5V I/O) Input High Voltage(2.5V I/O) VOL VOH VOL VOH VIL VIH VIL VIH All Inputs=fixed (VDD-0.2V or 0.2V) Device deselected, IOUT=0mA, ZZVDD-0.2V, f=Max, All InputsVIL or VIH IOL=8.0mA IOH=-4.0mA IOL=1.0mA IOH=-1.0mA -65 -75 -65 -75 Min -2 -2 2.4 2.0 -0.3* 2.0 -0.3* 1.7 Max +2 +2 300 280 140 130 100 60 0.4 0.4 0.8 VDD+0.3 0.7 VDD+0.3 mA mA V V V V V V V V 3 3 Unit A A mA mA 1,2 Notes
Device deselected, IOUT=0mA, ZZ0.2V, f=0,
Notes : The above parameters are also guaranteed at industrial temperature range. 1. Reference AC Operating Conditions and Characteristics for input and timing. 2. Data states are all zero. 3. In Case of I/O Pins, the Max. VIH=VDDQ+0.3V
VIH
VSS
VSS-1.0V 20% tCYC(MIN)
TEST CONDITIONS
(VDD=3.3V+0.165V/-0.165V,VDDQ=3.3V+0.165/-0.165V or VDD=3.3V+0.165V/-0.165V,VDDQ=2.5V+0.4V/-0.125V, TA=0to70C)
PARAMETER Input Pulse Level(for 3.3V I/O) Input Pulse Level(for 2.5V I/O) Input Rise and Fall Time(Measured at 20% to 80% for 3.3V I/O) Input Rise and Fall Time(Measured at 20% to 80% for 2.5V I/O) Input and Output Timing Reference Levels for 3.3V I/O Input and Output Timing Reference Levels for 2.5V I/O Output Load
* The above parameters are also guaranteed at industrial temperature range.
VALUE 0 to 3.0V 0 to 2.5V 1.0V/ns 1.0V/ns 1.5V VDDQ/2 See Fig. 1
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Nov. 2003 Rev 3.0
K7B803625B K7B801825B
Output Load(A)
256Kx36 & 512Kx18 Synchronous SRAM
Output Load(B), (for tLZC, tLZOE, tHZOE & tHZC) RL=50 +3.3V for 3.3V I/O /+2.5V for 2.5V I/O Dout 353 / 1538 319 / 1667
Dout Zo=50
30pF*
VL=1.5V for 3.3V I/O VDDQ/2 for 2.5V I/O
5pF*
* Including Scope and Jig Capacitance Fig. 1
AC TIMING CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0C to +70C)
PARAMETER Cycle Time Clock Access Time Output Enable to Data Valid Clock High to Output Low-Z Output Hold from Clock High Output Enable Low to Output Low-Z Output Enable High to Output High-Z Clock High to Output High-Z Clock High Pulse Width Clock Low Pulse Width Address Setup to Clock High Address Status Setup to Clock High Data Setup to Clock High Write Setup to Clock High (GW, BW, WEX) Address Advance Setup to Clock High Chip Select Setup to Clock High Address Hold from Clock High Address Status Hold from Clock High Data Hold from Clock High Write Hold from Clock High (GW, BW, WEX) Address Advance Hold from Clock High Chip Select Hold from Clock High ZZ High to Power Down ZZ Low to Power Up SYMBOL tCYC tCD tOE tLZC tOH tLZOE tHZOE tHZC tCH tCL tAS tSS tDS tWS tADVS tCSS tAH tSH tDH tWH tADVH tCSH tPDS tPUS -65 MIN 7.5 2.5 2.5 0 2.2 2.2 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 2 2 MAX 6.5 3.5 3.5 3.8 MIN 8.5 2.5 2.5 0 2.5 2.5 2.0 2.0 2.0 2.0 2.0 2.0 0.5 0.5 0.5 0.5 0.5 0.5 2 2 -75 MAX 7.5 3.5 3.5 4.0 UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns cycle cycle
Notes : 1. The above parameters are also guaranteed at industrial temperature range. 2. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP is sampled low and CS is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected. 3. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled. 4. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state.
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Nov. 2003 Rev 3.0
TIMING WAVEFORM OF READ CYCLE
tCH tCL
CLOCK
tSH tCYC
K7B803625B K7B801825B
tSS
ADSP
tSS tSH
ADSC
tAH A2 tWS tWH A3
BURST CONTINUED WITH NEW BASE ADDRESS
tAS
ADDRESS
A1
256Kx36 & 512Kx18 Synchronous SRAM
- 11 tCSH tADVS tADVH
(ADV INSERTS WAIT STATE)
WRITE
tCSS
CS
ADV
OE
tOE tHZOE tCD tOH Q2-1 Q2-2 Q2-3 Q2-4 Q3-1 Q3-2 Q3-3 Q1-1 tHZC Q3-4
tLZOE
Data Out
Dont Care Undefined
Nov. 2003 Rev 3.0
NOTES : WRITE = L means GW = L, or GW = H, BW = L, WEx.= L CS = L means CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L
TIMING WAVEFORM OF WRTE CYCLE
tCH tCL
CLOCK
tSH tCYC
K7B803625B K7B801825B
tSS
ADSP
tSS tSH
ADSC
tAH A1 A2
(ADSC EXTENDED BURST)
tAS
ADDRESS
A3 tWS tWH
WRITE
tCSH
256Kx36 & 512Kx18 Synchronous SRAM
- 12 (ADV SUSPENDS BURST)
tCSS
CS
tADVS tADVH
ADV
OE
tDS D1-1 tLZOE Q0-4 D2-1 D2-2 D2-2 D2-3 D2-4 D3-1 D3-2 tDH D3-3 D3-4
Data In
Data Out
Q0-3
Dont Care Undefined
Nov. 2003 Rev 3.0
TIMING WAVEFORM OF COMBINATION READ/WRTE CYCLE(ADSP CONTROLLED, ADSC=HIGH)
tCH tCL
CLOCK
tSS tSH tCYC
K7B803625B K7B801825B
ADSP tAS
tAH A2 A3 tWS tWH A1
ADDRESS
WRITE
CS
tADVS tADVH
256Kx36 & 512Kx18 Synchronous SRAM
- 13 tDS D2-1 tCD tLZC tHZOE Q1-1 tOE tLZOE Q3-1 tDH
ADV
OE
Data In
tHZC
tOH Q3-2 Q3-3 Q3-4
Data Out
Nov. 2003 Rev 3.0
Dont Care Undefined
TIMING WAVEFORM OF SINGLE READ/WRITE CYCLE(ADSC CONTROLLED, ADSP=HIGH)
tCH tCL
CLOCK
tSH tCYC
K7B803625B K7B801825B
tSS
ADSC
tWS A2 tWS tWH A3 A4 A5 A6 A7 A8 tWH A9
ADDRESS
A1
WRITE
tCSH
tCSS
CS
256Kx36 & 512Kx18 Synchronous SRAM
- 14 tOE tHZOE Q1-1 Q2-1 Q3-1 Q4-1 tDS D5-1 D6-1
ADV
OE
tCD Q8-1 tDH D7-1 tOH Q9-1
tLZOE
Data Out
Data In
Dont Care Undefined
Nov. 2003 Rev 3.0
TIMING WAVEFORM OF SINGLE READ/WRITE CYCLE(ADSP CONTROLLED, ADSC=HIGH)
tCH tCL
CLOCK
tCYC
K7B803625B K7B801825B
tSS
tSH
ADSP
tAS A2 A3 A4 A5 A6 A7 A8 tAH A9
ADDRESS
A1
WRITE
tCSS
tCSH
CS
256Kx36 & 512Kx18 Synchronous SRAM
- 15 tHZOE Q1-1 Q2-1 Q3-1 Q4-1 tDS D5-1 D6-1 tDH
ADV
OE
tCD Q8-1 tOH Q9-1
tOE
tLZOE
Data Out
Data In
D7-1
Dont Care Undefined
Nov. 2003 Rev 3.0
TIMING WAVEFORM OF POWER DOWN CYCLE
tCH tCL
CLOCK
tSH tCYC
tSS
K7B803625B K7B801825B
ADSP
ADSC
tAH A2 tWS tWH
tAS
ADDRESS
A1
WRITE
tCSH
tCSS
256Kx36 & 512Kx18 Synchronous SRAM
- 16 tOE tHZC Q1-1 tPDS
ZZ Setup Cycle Sleep State
CS
ADV
OE
Data In
tLZOE tHZOE
D2-1
D2-2
Data Out
tPUS
ZZ Recovery Cycle Normal Operation Mode
ZZ
Dont Care Undefined
Nov. 2003 Rev 3.0
K7B803625B K7B801825B
APPLICATION INFORMATION
DEPTH EXPANSION
256Kx36 & 512Kx18 Synchronous SRAM
The Samsung 256Kx36 Synchronous Burst SRAM has two additional chip selects for simple depth expansion. This permits easy secondary cache upgrades from 256K depth to 512K depth without extra logic.
Data Address
I/O[0:71] A[0:18] A[18] A[0:17] Address Data CS2 CS2 CLK Address CLK Cache Controller ADSC WEx OE CS1 ADV ADSP 256Kx36 SB SRAM (Bank 0) A[18] A[0:17] Address Data CS2 CS2 CLK ADSC WEx OE CS1 ADV ADSP 256Kx36 SB SRAM (Bank 1)
CLK
Microprocessor
ADS
INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing) (ADSP CONTROLLED , ADSC=HIGH)
CLOCK
tSS tSH
ADSP
tAS tAH A2 tWS tWH A1
ADDRESS [0:n] WRITE
tCSS
tCSH
CS1
Bank 0 is selected by CS2, and Bank 1 deselected by CS2
An+1
tADVS tADVH
Bank 0 is deselected by CS2, and Bank 1 selected by CS2
ADV
OE
tOE
Data Out (Bank 0) Data Out (Bank 1)
tLZOE
tHZC Q1-1 Q1-2 Q1-3 Q1-4 tCD tLZC Q2-1 Q2-2 Q2-3 Q2-4
Dont Care Undefined
*Notes : n = 14 32K depth , 16 128K depth , 18 512K depth
15 64K depth 17 256K depth
- 17 -
Nov. 2003 Rev 3.0
K7B803625B K7B801825B
APPLICATION INFORMATION
DEPTH EXPANSION
256Kx36 & 512Kx18 Synchronous SRAM
The Samsung 512Kx18 Synchronous Burst SRAM has two additional chip selects for simple depth expansion. This permits easy secondary cache upgrades from 512K depth to 1M depth without extra logic.
Data Address
I/O[0:71] A[0:19] A[19] A[0:18] A[19] A[0:18]
CLK
Address Data CS2 CS2 CLK Address CLK Cache Controller ADSC WEx OE CS1 ADV ADSP 512Kx18 SB SRAM (Bank 0)
Address Data CS2 CS2 CLK ADSC WEx OE CS1 ADV ADSP 512Kx18 SB SRAM (Bank 1)
Microprocessor
ADS
INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing) (ADSP CONTROLLED , ADSC=HIGH)
CLOCK
tSS tSH
ADSP
tAS tAH A2 tWS tWH A1
ADDRESS [0:n] WRITE
tCSS
tCSH
CS1
Bank 0 is selected by CS2, and Bank 1 deselected by CS2
An+1
tADVS tADVH
Bank 0 is deselected by CS2, and Bank 1 selected by CS2
ADV
OE
tOE
Data Out (Bank 0) Data Out (Bank 1)
tLZOE
tHZC Q1-1 Q1-2 Q1-3 Q1-4 tCD tLZC Q2-1 Q2-2 Q2-3 Q2-4
Dont Care Undefined
*Notes : n = 14 32K depth , 16 128K depth , 18 512K depth ,
15 64K depth 17 256K depth 19 1M depth
- 18 -
Nov. 2003 Rev 3.0
K7B803625B K7B801825B
PACKAGE DIMENSIONS
100-TQFP-1420A
22.00 0.30 20.00 0.20
256Kx36 & 512Kx18 Synchronous SRAM
Units ; millimeters/Inches
0~8
0.10 0.127 + 0.05 -
16.00 0.30 14.00 0.20 0.10 MAX
(0.83) 0.50 0.10 #1 0.65 0.30 0.10 0.10 MAX (0.58)
1.40 0.10 1.60 MAX 0.50 0.10 0.05 MIN
- 19 -
Nov. 2003 Rev 3.0

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